AMEC’s Six CSEAC 2026 Tools Show a Broader Equipment Platform

AMEC used CSEAC 2026 to present a portfolio rather than a single flagship machine. The official CSEAC announcement scheduled the Wuxi exhibition for 31 August to 2 September 2026. In its event recap, CSEAC named six products from AMEC spanning high-aspect-ratio etch, film deposition, integrated metal processing and silicon-carbide epitaxy.

The launch says more about breadth than a shared commercial stage. The South China Morning Post and Sina Technology each identified four of the six products as deposition tools. Their concentration around film formation changes the center of gravity of the release: AMEC is adding several routes into dielectric, metal and interface work at the same time that it pushes its established etch branch toward harder geometry.

Commercial progress is less uniform than the product map. AMEC has disclosed laboratory or customer-facing milestones for named etch and Uniflash programs, while the other launch names are defined mainly by their intended process roles. That unevenness is the platform story. XD-RIE deepens etch, the deposition group creates several adjacencies around advanced memory and logic, and PDS8 opens a silicon-carbide branch. AMEC now has named systems behind a multi-category strategy; their commercial depth will accumulate product by product.

Why this launch changes AMEC’s product story

Semiconductor-equipment companies are usually understood through the process category in which customers first learn to depend on them. That starting category influences technical reputation, account access, supplier relationships, field-service experience and the kinds of engineering problems the organization is prepared to solve. In its 2 September 2026 report, SCMP described etching as AMEC’s core business and the company as moving from an etching specialist toward a broader equipment supplier. CSEAC 2026 made that broadening concrete by placing dielectric and metal deposition, interface preparation and SiC epitaxy beside the etch product in one release.

The shift matters because equipment categories are not interchangeable labels. An etcher controls how material is removed from a patterned structure. A deposition system controls how a film forms on surfaces that may be deep, narrow or materially complex. An integrated preclean-and-deposition system controls the condition of an interface as well as the films placed above it. A SiC epitaxy reactor grows crystalline material under a different thermal and material regime. Moving across those jobs requires distinct chamber designs, recipes and application knowledge.

“Platform” therefore describes an organization carrying several specialized product programs at once. It does not require the six machines to share one chamber architecture or one process recipe. The common layer sits around the process modules: product development, controls, component engineering, manufacturing, installation, service and the movement of customer feedback back into design. The category-specific layer remains with the physics of etch, film formation, interface control or crystal growth.

The launch expands AMEC at three connected levels. First, it attaches product names to a broader set of process jobs, turning a general expansion strategy into a visible portfolio. Second, it gives AMEC more potential contact points inside memory and power-semiconductor manufacturing. Third, it tests whether the company can keep specialized teams moving through development and customer work without losing the repeatability expected from an equipment supplier.

Most of the release is concentrated rather than scattered. XD-RIE and the deposition systems gather around difficult structures, films and interfaces in advanced devices, especially three-dimensional memory. Their process roles differ, but the output of one step can become the starting condition for another. PDS8 follows a separate SiC path. That shape matters: AMEC is combining deeper etch work, adjacent expansion around memory, and a new material branch rather than adding six unrelated names.

Those three forms of expansion carry different organizational distances. Category deepening can draw most directly on existing etch knowledge, customer conversations and service habits, even as the targeted geometry becomes harder. Process adjacency keeps AMEC near related device structures but asks new teams to earn credibility for different films and interfaces. The SiC branch carries the development system into another material environment and a different set of process priorities. Seeing those distances makes the portfolio easier to judge: the launches share a corporate engine, yet each asks AMEC to transfer a different amount of knowledge while building new expertise. A platform becomes consequential when it can manage all three forms without treating their technical or commercial paths as identical.

Six launches arranged around process problems

The six names make more sense as a process map than as a catalogue:

The lineup divides equipment work into five different objects of control: deep etched geometry, dielectric stacks, conductive fill, prepared metal interfaces and epitaxial crystal growth. QuaStar ON and GE share a family name but start from different application definitions. Unicore AM combines a wafer format, material, deposition method and memory role. Uniflash is defined by the connection among three process steps, while PDS8 combines a new material system with a high-temperature reactor format. Those differences determine what each engineering team must stabilize and what a customer can evaluate.

Commercial depth grows through several transitions. A launch fixes the intended application and product boundary; customer work then attaches that proposition to actual facilities, wafers, recipes and acceptance requirements. Production use adds repeated lots, changing chamber or reactor conditions and maintenance. Further deployment shows whether a result can be carried into more tools, lines, sites or applications.

As of 4 September 2026, AMEC’s H1 2026 product-progress section names Primo XD-RIE itself: the Alpha machine had completed a laboratory marathon test, while the Beta machine was progressing through client validation. For Uniflash, AMEC reported at a broader level. The Preforma Uniflash metal-silicide integration family, including SPTi and ALD TiNM modules, had been delivered to multiple advanced-logic and advanced-memory clients, with on-site validation progressing. That status belongs to the family and named modules rather than the CSEAC SPTi/TiN configuration itself. The filing gives no comparable product-level stage detail for QuaStar ON, QuaStar GE, Unicore AM or PDS8.

The six machines therefore combine two dimensions that can move at different speeds. Product definition becomes sharper as a family name is tied to a film, structure, interface or material system. Operating depth grows as that bounded result survives more wafers, process variation and maintenance. One application can advance without carrying every use under the same family name with it, and progress in one product category does not transfer automatically to another.

In the wider progression for Chinese semiconductor equipment, launch, customer validation, production use and repeat deployment mark increasingly durable supplier positions. CSEAC made AMEC’s intended breadth visible. The named H1 milestones show that parts of the portfolio have entered laboratory and customer work, but the position of each branch still depends on the result being pursued inside it.

XD-RIE deepens the etch branch

At CSEAC 2026, TrendForce described Primo XD-RIE as targeting a 70:1 to 90:1 aspect-ratio range. Aspect ratio relates feature depth to feature width, so the range points to deep structures reached through comparatively narrow openings. The test structure, material, selectivity and measurement method behind the reported range were not specified, making it a target for a process regime rather than a like-for-like benchmark against another tool.

That regime turns etch into a coupled control problem. Plasma conditions have to remove material at the bottom of a narrow feature while preserving the opening and sidewalls above it. More aggressive removal can change etch rate, selectivity or profile, and a condition that works at one pattern density may behave differently elsewhere on the wafer. As the chamber surface changes with use, the recipe and hardware have to keep that balance inside the customer’s limits.

Depth makes small deviations consequential. Reactive species must travel farther into the feature, reaction products must leave it, and charging can affect different parts of the structure. The useful result is a combination: the target depth is reached, the intended material is removed relative to its neighbors, the sidewalls and opening retain the required profile, and defects stay controlled across the wafer. A headline ratio identifies the geometry challenge but cannot replace those interacting results.

Absolute dimensions add another layer. Two structures can share the same depth-to-width ratio while having different openings, transport distances and material-removal loads. Pattern density and the surrounding film stack can also change how one recipe behaves across a wafer. XD-RIE’s 70:1 to 90:1 territory becomes an operating result only when it is tied to an actual feature, material stack and acceptance method.

The commercial object is therefore a process window rather than a peak ratio. A useful window absorbs variation in incoming wafers, pattern density and chamber condition while keeping profile, selectivity and defect control within specification. Gas delivery, plasma control, wafer temperature, chamber surfaces and cleaning all contribute to that window. Customer work brings them together around the customer’s structure rather than a generic deep opening.

That process window also determines the support burden carried by the machine. When a result moves, the equipment team has to distinguish among incoming material, pattern design, recipe, chamber hardware and the state left by earlier runs. A stable operating method lets those causes be separated and corrected without treating every deviation as the same problem. For XD-RIE, that diagnostic discipline is part of extending etch expertise into a geometry where small changes at the top, sidewall or bottom can have different consequences.

For AMEC, XD-RIE represents category deepening rather than category addition. The company is applying its etch development program to a more demanding geometry while the rest of the CSEAC portfolio builds positions around it. That gives the expansion a technical center: breadth is not being used as a substitute for advancing the etch process itself.

Etch also connects the product map to later steps. The geometry left by XD-RIE becomes a surface on which dielectric or conductive films may have to form. Changes in sidewall condition or feature profile can alter the challenge faced by deposition. This does not turn the tools into one process platform, but it places their application teams around related integration questions and gives customer feedback from one module potential relevance to another.

Four deposition systems divide the film problem

The deposition-heavy middle of the release contains four propositions, not four copies of one chamber. QuaStar ON and GE form a named family with different degrees of application specificity. Unicore AM centers on one metal and one memory role. Uniflash centers on an interface and a connected sequence of preparation and film formation. Together they show how AMEC is breaking the broad word “deposition” into distinct customer problems.

All four share one operating baseline. A film or interface recipe has to hold thickness, uniformity, composition, stress, particle behavior and electrical function within the needs of the surrounding structure. The system then has to reproduce that result across processing positions, wafers, chamber condition, cleaning and maintenance. That common discipline links the products, but the object being controlled—and therefore the commercial question—changes from one family to the next.

QuaStar: one family, two dielectric paths

For QuaStar ON, TrendForce’s CSEAC 2026 account describes a PECVD system for SiO/SiN stacks in 3D NAND, with up to 16 wafers in one system. The application and configuration answer different engineering questions. The SiO/SiN stack locates the system in repeated dielectric-film work for three-dimensional memory; the wafer count describes how much processing capacity is arranged inside the reported system.

The stack gives QuaStar ON a relatively narrow starting point. Each layer must meet its own film targets while remaining compatible with the larger repeated structure. Thickness and composition influence the intended dielectric function, stress can accumulate through the stack, and particles or drift can affect many layers rather than one isolated surface. The system-level challenge is to keep those film results compatible across its processing resources as recipes, cleaning and chamber condition change.

QuaStar GE broadens the family’s application range. Sina Technology’s CSEAC 2026 report describes silicon-based dielectric-film work for both memory and logic, with up to 12 wafers processed in one system. Where ON starts from a named 3D-NAND SiO/SiN stack, GE starts from a wider material and application remit that can lead to several distinct customer recipes.

The 16-wafer ON and 12-wafer GE figures are per-system capacity descriptions, not wafers-per-hour rates. Neither report gives the cycle time, uptime or recipe conditions needed to turn those capacities into comparable throughput, and neither supplies a wafer diameter for the stated capacity. The figures describe how the two products were configured at launch; useful output depends on the films produced while those resources are loaded and operated.

A multi-resource dielectric system also creates a coordination problem beyond the result on one wafer. Recipe duration affects how wafers move through the machine, chamber cleaning changes resource availability, and chamber matching determines whether processing positions can be used as one coherent system. The operational aim is not simply to keep every position busy. It is to combine film quality, scheduling and maintenance so the configuration produces a predictable stream of usable wafers for the selected stack.

That leaves the two family members with different first commercial questions. For ON, the task can narrow around whether the configured system produces the required SiO/SiN stack with compatible results across processing positions and over operating cycles. For GE, the first step is to bind the broad dielectric proposition to a particular film, substrate condition, surrounding process and acceptance target. ON begins with application depth; GE begins with application choice.

The shared QuaStar name can still matter operationally. Controls, wafer handling, maintenance practices and lessons about chamber matching may travel across a family even when recipes and acceptance criteria do not. That gives AMEC a way to build a wider dielectric offering without pretending that success on one film settles another. The commercial value of the family will come from how often those shared systems help specialized film programs reach stable customer use.

Unicore: molybdenum fill inside a memory structure

The official CSEAC 2026 recap describes Prefima Unicore AM as a 12-inch ALD molybdenum tool for word-line fill in ultra-high-stack 3D memory. The description identifies wafer size, deposition method, material and process role together. Unicore is aimed at the conductive part of a memory structure, giving it a narrower task than GE’s broader dielectric remit.

Atomic layer deposition is relevant to the way that metal must form through demanding geometry. Repeated surface-controlled steps shape how the film nucleates and extends over the available surfaces. Coverage has to develop into a continuous conductive feature, while impurities, thickness and the interface with neighboring materials influence the electrical result.

The incoming geometry links Unicore back to the rest of the memory-centered portfolio. A word-line feature presents surfaces created and conditioned by earlier steps, so molybdenum formation has to fit the opening and neighboring materials it receives. Coverage that is adequate near the entrance may still leave a weak region deeper in the structure, while a change that improves continuity can alter thickness, impurities or resistance. The process is judged as a conductive feature inside the device stack, not as an isolated blanket film.

That makes resistance and integration as important as the presence of molybdenum. A film may look acceptable in isolation yet fail to meet the electrical or geometric needs of the word line. The deposition sequence also consumes time, so the process must balance the cycles needed for formation and coverage against an operating rhythm the application can sustain.

Unicore’s commercial question is correspondingly specific: can the molybdenum process fill the intended word-line geometry and meet its electrical and integration requirements on the named 12-inch wafer format? ALD identifies how the film is formed, molybdenum identifies the conductor, and word-line fill identifies the function. The product earns depth when those coordinates work together as one usable process rather than as separate specifications.

Uniflash: preserving an interface across three connected steps

The official CSEAC 2026 recap describes Preforma Uniflash SPTi/TiN as combining three process steps: in-situ preclean, Ti PECVD and TiN ALD. Its proposition begins before film deposition. Preclean prepares the starting surface, titanium forms the next part of the interface, and titanium nitride completes the reported sequence within the integrated system.

The connection among those steps is the product. Surface condition after preclean affects how Ti forms; the Ti result becomes the starting condition for TiN; transfers and timing determine what reaches each chamber. Bringing the sequence into one system gives the equipment team a coordinated interface problem instead of three isolated film results.

That coordination changes how the process can be tuned. The endpoint of preclean has to be chosen for the surface the Ti step needs, and the Ti recipe has to leave the condition required by TiN. Transfer time becomes part of the recipe because the prepared surface can change between chambers. The strongest operating window is therefore one in which nearby adjustments do not push the final interface outside its electrical and integration targets.

Integration also multiplies interactions. Chamber matching, contamination control, recipe timing and wafer transfer can influence the final interface even when each module reaches its individual target. A change meant to improve preclean can alter Ti nucleation, and an adjustment to Ti can change the surface presented to the TiN step. The useful process window belongs to the sequence as well as to each module.

Fault isolation becomes part of the engineering proposition. If the final interface drifts, the cause may sit in preclean, Ti formation, TiN formation, a transfer or the way one step changes the next. After maintenance, recovery means bringing the connected sequence back into alignment. That requires diagnostic information that can separate a module problem from an interaction among modules.

Uniflash therefore carries two linked commercial questions: whether each module performs its assigned job and whether the full flow preserves the intended interface through ordinary operation and interruption. Its three-step count is a process architecture, while the customer result sits at the end of the coordinated flow. That is a different responsibility from supplying a single deposition chamber.

Taken together, the four systems show why adjacency is more valuable than simple product accumulation. In a three-dimensional structure, etch creates geometry; dielectric deposition builds insulating layers; metal deposition creates conductive features; cleaning and barrier-related films shape interfaces. Incoming geometry constrains film formation, and each deposited material changes the conditions faced by later process steps.

The handoffs create useful learning loops without making the tools interchangeable. An etch team may identify a sidewall or profile condition that changes film behavior; a dielectric team may expose stress or particle requirements for a repeated stack; a metal team may identify an interface that constrains an earlier clean. AMEC can translate those observations into product specifications and coordinated support while each process team remains responsible for its own result.

This is the strongest platform signal in the launch. QuaStar combines family-level operating commonality with two dielectric paths, Unicore moves into a defined conductive role, and Uniflash makes interface coordination the product itself. Their technical objects and customer milestones differ, but they give AMEC several related positions around the structures that dominate the memory-centered part of the release.

PDS8 opens a separate SiC branch

Sina Technology’s CSEAC 2026 report describes PRISMO PDS8 as a high-temperature SiC epitaxy system supporting up to four 8-inch wafers simultaneously. This product sits outside the tight memory-centered group. It extends AMEC into compound-semiconductor crystal growth and toward power-semiconductor manufacturers whose material and process priorities differ from those around silicon memory.

That configuration describes reactor loading, not acceptable wafers per hour. Cycle time, reactor availability, maintenance and the material quality achieved at all four positions determine how that loading becomes useful output. The distinction is especially important here because increasing the number of wafers in a run also increases the area and number of positions over which conditions must remain controlled.

Multi-wafer epitaxy creates two linked uniformity problems. Each wafer needs acceptable material across its own surface, and the four positions need results close enough to function as one load. Thermal conditions, gas flow, cleanliness and the changing state of internal surfaces can affect thickness and doping across both dimensions. A system-wide average can hide an outlying wafer or a position that drifts as the reactor changes through use.

The spatial pattern of a result can help locate the engineering problem. Variation across one wafer may point toward how heat or gas is distributed over that position; a difference among positions may point toward the way the loaded reactor is balanced. Changes from run to run add the condition of internal surfaces and the maintenance cycle. PDS8 must bring those views together so material quality can be traced to the reactor state that produced it and restored after intervention.

Crystal quality adds another axis to the operating result. Defects, wafer bow and variation can affect how the epitaxial material proceeds into later device work. PDS8’s customer problem therefore joins material targets to reactor behavior: the system has to produce the required epitaxial layer at each position, sustain the result across runs and recover it after maintenance.

This branch extends more than AMEC’s hardware catalogue. Application support has to work in the language of epitaxial growth, while field service has to understand a high-temperature reactor and its maintenance cycle. Component choices and chamber conditioning follow SiC requirements rather than the plasma-etch or thin-film priorities around advanced memory. Company-wide manufacturing and service systems may be shared, but the process expertise has to be built around a different material environment.

PDS8 is consequently the longest organizational step in the six-tool release. The memory-centered products can meet around related structures and interfaces; PDS8 has to establish a second technical center with a different material system and customer base. Its progress can move on its own schedule. The platform value lies in AMEC’s ability to support that separate branch while continuing to deepen etch and deposition, not in forcing all six tools into one timetable.

The portfolio has a development engine behind it

The event lineup is one visible slice of a larger R&D program. In H1 2026, compared with H1 2025, AMEC reported R&D expenditure of RMB 2.041 billion, up 36.86% year on year and equal to 30.51% of H1 2026 revenue. The period and denominator matter: the amount covers the first half of 2026, the growth rate compares it with H1 2025, and the revenue share uses the company’s H1 2026 revenue.

For the same H1 2026 disclosure, AMEC said its R&D program covered six equipment categories and more than 20 tools in development. That count is a picture of the development queue, where projects can occupy different stages. Its denominator is tools in development; launched or qualified tools are different measures.

Together, the two figures describe scale from different directions. Spending measures resources committed during a defined reporting period; the program count measures the breadth of work being carried at that point. The pair says more about AMEC’s development capacity than either number alone. A large budget without named process programs would reveal little about where the effort was going, while a long project list without the spending context would reveal little about the resources available to move it forward.

The platform question turns on how those resources are converted. Some organizational capabilities can serve several families: controls and software practices, component engineering, manufacturing quality, documentation, installation routines, parts logistics and the systems used to return field observations to product teams. The process knowledge remains specialized. An etch profile, a dielectric stack, a molybdenum fill, an integrated metal interface and SiC epitaxial material each require their own chamber decisions, recipes and acceptance conditions. Manufacturing, service and customer feedback belong to one operating loop here: build the intended configuration consistently, support it in use, identify whether a result comes from recipe, hardware or surrounding conditions, and carry a controlled improvement into the next machine. The shared organization has value when it strengthens that specialized work rather than flattening it.

A program this broad also creates an allocation problem. Engineers, test capacity, suppliers, manufacturing attention and field-support resources have to move toward products at different stages without allowing the most mature branch to absorb every shared function. The etch team can contribute methods for chamber control or service response, but deposition and epitaxy teams still need room to develop their own process knowledge. Platform management is the work of making common systems economical while keeping category-specific decisions close to the specialists who understand them.

This reading also gives the R&D ratio a practical meaning without turning spending into a capability score. RMB 2.041 billion and 30.51% of H1 revenue show the intensity of resource allocation in the first half of 2026. The six-category, 20-plus-tool program shows how many fronts could draw on it. Commercial capability appears only as those inputs become reproducible designs, bounded customer processes and supportable machines. CSEAC supplied visible outputs from that engine; continued product-level progress will show how efficiently the engine converts scale of effort into durable equipment positions.

Repeat deployment across categories is the durable-platform test

The strongest commercial test of AMEC’s broader platform is follow-on deployment in more than one equipment category. Additional use in etch would deepen the company’s anchor, but a second cycle of adoption in another category would show that AMEC can reproduce the path from product definition to customer operation with a different process team. The timing need not be synchronized. What matters is repeated conversion across distinct technical fields rather than a larger catalogue moving as one batch.

What must repeat is the operating relationship around the tool. A customer process has to remain within its acceptance window as wafers, chamber or reactor condition and maintenance events accumulate. Manufacturing must deliver the intended configuration consistently; field service must restore it after intervention; application teams must turn operating feedback into controlled changes. Follow-on deployment indicates that those pieces worked together well enough for the customer to extend its use of the supplier.

Cross-category repetition is a higher bar because process physics and support needs differ. Etch, deposition and epitaxy cannot share one recipe or one acceptance test, yet they can draw on common controls practices, component engineering, manufacturing quality, installation routines, parts logistics and feedback systems. If customers return for tools in at least two categories, those shared functions are strengthening specialized process programs instead of merely sitting above them as corporate infrastructure.

The pattern would also change AMEC’s commercial resilience. A platform with durable positions in several categories has more than multiple products: it has several routes into customer work and more than one source of operating feedback. Problems discovered in one category still require category-specific solutions, but the organization can improve how it builds, installs, diagnoses and supports equipment across the portfolio. That is the practical advantage breadth is meant to create.

The broader China semiconductor industry guide places process equipment inside the full chain of materials, design, fabrication, packaging and testing. CSEAC shows that AMEC now addresses a wider set of positions within the equipment layer. Repeat deployment across more than one of those positions would turn breadth into a demonstrated commercial pattern.

For now, “platform expansion in progress” remains the strongest judgment. The six launches make the expanded architecture visible, and the disclosed customer work shows movement beyond announcement. A durable platform will be present when AMEC can win, support and extend customer use across multiple equipment categories—not merely introduce them together.

Related reading

• Chinese Semiconductor Equipment: The Buyer File
• China’s Semiconductor Industry: A Layer-by-Layer Guide